A semiconductor device is equipped with a reference voltage generating circuit that generates a reference voltage for reference. For example, in semiconductor memory devices, a reference voltage is used to write data into memory cells and is used to generate a voltage used for reading. It is thus required that the reference voltage generating circuit is capable of quickly generating the reference voltage substantially immune to temperature changes and variations in the power supply voltage.
FIG. 1 (Prior Art) is a diagram of a circuit configuration of a reference voltage generating circuit 70 according to a first conventional art. Referring to this figure, a P-FET 71, a resistor R71 and an N-FET 72 are connected in series between a power supply Vcc and ground. The FET 71 functions as a switch for activating the reference voltage generating circuit 70 in response to ENFVREFB. The gate and drain of FET 72 are short-circuited. An output node N71 is provided between the resistor R71 and FET 72, and a reference voltage FBREF is available via the output node N71. In the first conventional art, the power supply Vcc is divided by the resistor R71 and FET 72 to thus generate the reference voltage FVREF.
FIG. 2 (Prior Art) is a diagram of a circuit configuration of a reference voltage generating circuit 80 (second conventional art) disclosed in Document 1 (Japanese Utility Model Application Publication No. 56-4266). The reference voltage VREF is output via an output node N81 provided between an N-FET 85 and an N-FET 86 connected between a power supply VD and ground. The FET 86 has gate and drain that are short-circuited, and functions as a diode. Resistors R81 and R82 are disposed between the power supply VD and the ground, and a voltage VR obtained by dividing the power supply voltage VD by the resistors R81 and R82 is available via the node N82. VREF and VR are applied to a differential amplifier 84. The differential amplifier 84 has P-FETs 81 and 82, and N-FETs 83, 84 and 88. The FET 88 is a current source for the differential amplifier 84, and the gate of the FET 88 is connected to the power supply VD. The output of the differential amplifier 84 is connected to the gate of FET 85.
In the reference voltage generating circuit 80 of the second conventional art, the resistors R81 and R82 are designed to have given values that define a desired value of VR. When VREF is higher than VR, a decreased current flows through FET 85 and the VREF is reduced. In contrast, when VREF is lower than VR, an increased current flows through FET 85 and the VREF is increased. In this manner, the reference voltage VREF is maintained at the constant level.
The reference voltage generating circuit 70 of the first conventional art is capable of generating the stabilized reference voltage shortly after the operation signal FNFVREFB is applied. Further, the reference voltage is stable to temperature changes. However, when the power supply Vcc varies, the reference voltage VFREF changes greatly. It is difficult to generate the reference voltage stable to variations in the power supply voltage in the reference voltage generating circuit capable of quickly generating the reference voltage stable to temperature changes.
The reference voltage generating circuit 80 of the second conventional art has an arrangement such that the power supply VD is applied to the gate of the current source FET 88 of the differential amplifier 84. However, the differential amplifier 84 is also supplied with the voltage VR generated by dividing the power supply voltage VD by the resistors. Thus, only limited feedback control to variations in the power supply voltage VD is available.